1. Technical Field
The present invention relates to a frequency synthesizer for reducing noise, and more particularly, to a phase locked loop (PLL)-based fractional-N frequency synthesizer.
2. Description
Recently, frequency synthesizers use a fractional-N phase locked loop (PLL) to the locking time.
A sigma delta modulator is commonly used in the fractional-N PLL. The sigma delta modulator generates a selection signal that is used to select the division ratio (divisor) of a divider of the frequency synthesizer. The division ratio (divisor) of the divider is randomly selected using the selection signal generated by the sigma delta modulator. If the division ratio of the divider is selected at regular intervals using the selection signal, frequency spurs can occur in an output spectrum. That is, the sigma delta modulator serves to select the division ratio of the divider and serves to shape noise.
The amount of area of a chip that is required by the sigma delta modulator is large, but this problem can be solved using a sigma delta modulator which generates a 1-bit selection signal.
FIG. 1 is a block diagram illustrating the structure of a fractional-N frequency synthesizer. Referring to FIG. 1, the fractional-N frequency synthesizer 100 includes a first divider 110 which receives and divides an oscillation frequency signal FOSC and generates a reference frequency signal FR, a second divider 120 which receives and divides a feedback frequency signal FVCO and generates a comparison frequency signal FP, and a sigma delta modulator 130.
A phase frequency detector which receives the reference frequency signal FR and the comparison frequency signal FP and compares the phase of the reference frequency signal FR with the phase of the comparison frequency signal FP, a charge pump, and a low pass filter are not shown.
The division ratio (divisor) of the first divider 110 is R. The division ratio (divisor) of the second divider 220 is selected as one of N−1 or N+1 in response to a selection signal SEL.
The sigma delta modulator 130 generates the selection signal SEL and randomly selects the division ratio of the second divider 120. The capacity of the sigma delta modulator 130 is marked by a partial modulus F. The partial modulus is a dimensionless quantity.
The sigma delta modulator 130 receives a predetermined value K and controls the selection signal SEL according to the value of K/F. An accumulator (not shown) is provided inside the sigma delta modulator 130. When the accumulator over-flows, that is, when the value of the inputted K reaches the value of the partial module F, the selection signal SEL selects the division ratio (divisor) of the second divider 120 to be N+1.
The second divider 120 divides the frequency of the input signal, FVCO, by an average value of (N+.f) in response to the selection signal SEL. Here, N represents an integer, and .f represents a decimal.
In the fractional-N frequency synthesizer 100 of FIG. 1, the feedback frequency signal FVCO is determined by the following equations:
Reference frequency signal FR=Oscillation frequency signal FOSC/R;
Comparison frequency signal FP=Feedback frequency signal FVCO/(N+.f).
Here, reference frequency signal FR=comparison frequency signal FP, and thus feedback frequency signal FVCO=reference frequency signal FR×(N+.f).
Thus, a desired feedback frequency signal FVCO can be made according to values of N and .f. Here, the feedback frequency signal FVCO is equal to an output frequency signal of the frequency synthesizer.
When the division ratios of the second divider 120 are N and N+1, a quantization level A is 1. The quantization level A represents a difference between the division ratios N+1 and N.
When the quantization level A is 1, the value of K inputted to the sigma delta modulator 130 cannot exceed about 80% of the value of the partial module F. This problem causes the output range of the output frequency signal to correspond to about 80% of a desired output range.
For example, when the output range of the desired output frequency signal is between 100 and 101 and the quantization level A is 1, the comparison frequency signal FP can be outputted within the range between 100.1 and 100.9 and cannot be outputted within the range between 100 and 100.1 and between 100.9 and 101. This problem is referred to as a “dead band problem.”
In order to solve the dead band problem, the division ratios of the second divider 120 are N−1 and N+1, as shown in FIG. 1. Then, the quantization level Δ is 2. Thus, the value of K inputted to the sigma delta modulator 130 when the quantization level Δ is 1. Therefore, the dead band problem of the output frequency signal is solved.
However, since the quantization level Δ is 2, a quantization noise power increases.
The quantization noise power may be expressed by Equation 1.P=Δ2/(12×OSR)  (1)
Here, P represents a quantization noise power, A represents a quantization level, and OSR represents an over sampling ratio.
As known from Equation 1, in order to reduce the quantization noise power, the quantization level should be reduced. Thus, a fractional-N frequency synthesizer which reduces the quantization noise power by setting the quantization level to 1 and generates an output frequency signal of a desired overall range is necessary.
To solve the above and other problems, it would be desirable to provide a fractional-N frequency synthesizer which exhibits reduced quantization noise power and generates an output frequency signal of a desired overall range.
It would also be desirable to provide a method for generating a frequency which exhibits reduced quantization noise power and generates an output frequency signal of a desired overall range.
Accordingly, in one aspect of the present invention, there is provided a frequency synthesizer, including a first divider, a second divider, and a division ratio (divisor) controller. The first divider receives and divides an oscillation frequency signal. The second divider receives a predetermined feedback frequency signal and divides the feedback frequency signal in response to a selection signal.
The division ratio controller receives and divides an output signal of the first divider and an output signal of the second divider and generates a reference frequency signal in which the oscillation frequency signal is divided, a comparison frequency signal that is compared with the reference frequency signal, and the selection signal used to select the division ratio of the second divider.
Beneficially, the division ratio controller includes a third divider, an internal division ratio controller, a sigma delta modulator, and a synthesizer.
The third divider receives and divides the output of the first divider and generates the reference frequency signal. The internal division ratio controller receives the output of the second divider and generates a 1-bit first selection signal used to generate the comparison frequency signal and the selection signal.
The sigma delta modulator receives a predetermined value K that is externally controlled and generates a 1-bit second selection signal used to generate the selection signal, in response to the comparison frequency signal.
The synthesizer synthesizes the selection signal from the first and second selection signals.
More specifically, the internal division ratio controller includes a first internal divider, a second internal divider, and a modulus controller.
The first internal divider receives and divides the output signal of the second divider and generates the comparison frequency signal. The second internal divider receives and divides the output signal of the second divider.
The modulus controller receives the comparison frequency signal and the output signal of the second internal divider, outputs the first selection signal as a first level when the first and second internal dividers are simultaneously being counted, and outputs the first selection signal as a second level when only the first internal divider is being counted.
The third divider and the first internal divider have the same division ratio (divisors), and the first and second internal dividers have the same counting period, and a counting operation time of the second internal divider is shorter than that of the first internal divider.
The ratio of divisor for the second internal divider to the divisor of the first internal divider is greater than or equal to 0 and less than 1.
The second selection signal has the first or second level at irregular intervals. The size of an accumulator provided inside the sigma delta modulator is denoted by F, and the sum of a value K/F and the ratio of the divisor of the second divider to the divisor of first divider is greater than or equal to 0 and smaller than 1.
The selection signal is a 2-bit signal which selects various division ratios (divisors) of the second divider.
According to another aspect of the present invention, there is provided a frequency synthesizer including a first divider, a second divider, a division ratio (divisor) controller, and a sigma delta modulator.
The first divider receives and divides an oscillation frequency signal. The second divider receives a predetermined feedback frequency signal and divides the feedback frequency signal by various division ratios in response to a selection signal.
The division ratio controller receives and divides an output signal of the first divider and an output signal of the second divider and generates a reference frequency signal in which the oscillation frequency signal is divided, a comparison frequency signal that is compared with the reference frequency signal, and a first selection signal that is used to generate the selection signal used to select the division ratio of the second divider.
The sigma delta modulator receives a predetermined value K that is externally controlled and generates a second selection signal used to generate the selection signal, in response to the comparison frequency signal.
The division ratio controller includes a third divider and an internal division ratio (divisor) controller.
The third divider receives and divides the output of the first divider and generates the reference frequency signal. The internal division ratio controller receives the output of the second divider and generates the comparison frequency signal and the first selection signal used to generate the selection signal.
More specifically, the internal division ratio controller includes a first internal divider, a second internal divider, and a modulus controller.
The first internal divider receives and divides the output signal of the second divider and generates the comparison frequency signal. The second internal divider receives and divides the output signal of the second divider.
The modulus controller receives the comparison frequency signal and the output signal of the second internal divider, outputs the first selection signal as a first level when the first and second internal dividers are simultaneously counted, and outputs the first selection signal as a second level when only the first internal divider is counted.
The first and second internal dividers have the same counting period, and a counting operation time of the second internal divider is shorter than that of the first internal divider.
The ratio of the divisor of the second internal divider to the divisor of the first internal divider is greater than or equal to 0 and less than 1.
The third divider and the first internal divider have the same division ratio (divisor), and the second selection signal has the first or second level at irregular intervals.
The selection signal is a 2-bit signal, each of the first and second selection signals is a 1-bit signal, the first and second selection signals are added together, thus generating the selection signal.
The size of an accumulator provided inside the sigma delta modulator is marked by F, and the sum of a value K/F and the ratio of the divisor of the second divider to the divisor of the first divider is greater than or equal to 0 and smaller than 1.
In yet another aspect of the invention, there is provided a method for generating an output frequency signal of a desired range while reducing a quantization noise power in a fractional-N frequency synthesizer having a sigma delta simulator. The method comprises: (a) dividing an oscillation frequency signal by R, dividing the R-divided oscillation frequency signal by D, and outputting a reference frequency signal; (b) receiving a predetermined feedback frequency signal and dividing the feedback frequency signal by various division ratios in response to a selection signal; (c) receiving and dividing the divided signal in (b), generating a comparison frequency signal that is compared with the reference frequency signal, and generating a 1-bit first selection signal used to generate the selection signal; (d) receiving a predetermined value K that is externally controlled and generating a 1-bit second selection signal used to generate the selection signal, in response to the comparison frequency signal; and (e) synthesizing the selection signal from the first and second selection signals and generating.
Step (c) comprises: (c1) dividing the divided signal in (b) by D, and generating the comparison frequency signal; (c2) dividing the divided signal in (b) by C; and (c3) receiving the comparison frequency signal and the output signal in (c2) and generating the first selection signal as a first or second level.
More specifically, in (c3), the comparison frequency signal and the output signal in (c2) are received, the first selection signal is outputted as the first level when (c1) and (c2) are simultaneously being performed, and the first selection signal is outputted as the second level when only (c1) is being performed.
A value C/D is greater than or equal to 0 and less than 1, and the second selection signal has the first or second level at irregular intervals. The selection signal is a 2-bit signal which selects various division ratios of (b).